CPU/Mobo IBM's POWER6 design

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Skilled
An eCLipz Looms on the Horizon

By: David Kanter (dkanter@realworldtech.com)
In the Shadow of Poughkeepsie

Since the release of the POWER5 MPU, IBM has held an enviable position in the high end server market. IBM’s pSeries servers are unmatched from a performance standpoint, boasting a 2x performance lead over the nearest competitor in TPC-C and within 5% of the #1 SAP 2D result (which is for a system with twice as many cores). This was achieved by strategically focusing on system level design, and migrating mainframe technologies, such as the 70 layer ceramic MCMs to the POWER4 and POWER5. As a result of this strong product line performance and consistent execution, IBM has been able to rapidly expand server market share, largely to the detriment of Sun Microsystems.

While IBM has made some improvements since the POWER5, the sheer magnitude of the performance lead has given IBM the option of a more leisurely pace of development. According to roadmaps, the POWER5+ was supposed to hit 2.3GHz in 2005. However, with the delay and revised expectations for Montecito, that clock speed boost is probably not needed till mid-2006.

Far from sitting on its laurels, IBM is actively working on the next two generations of their POWER based servers. In fact, the POWER6 has already taped out and the first samples have returned from the fab and are running. This generation of MPUs will be far more interesting than the prior generation, which was largely a refinement and improvement upon the POWER4. The POWER6 is also referred to as part of the eCLipz project, an acronym that stands for “enhanced Core logic for iSeries, pSeries and z Series” (thanks to Philip Payne of Isham Research for that tidbit).

IBM has been rather quiet about the eCLipz project and future POWER and mainframe (zSeries) processors, which has lead to rampant speculation. Naturally most of these theories are extremely dubious, such as a system using coherent interconnects between zArch and POWER processors. However, some of the rumors probably have a micro-kernel of truth to them. Hopefully this article will bring together some of truth out there and avoid the fictitious, fantastical and unlikely. In particular, this article will focus on facts and informed speculation about the nature of the eCLipz project, the upcoming POWER6 MPU and its performance characteristics.

contd at RWT

it's rather strange that IBM has narrowed down the processor width since the POWER5 (only half as wide) and made the pipeline longer for some g1g4h3rtz. They're looking at a 4.4+ GHz clockspeed. The chip also sports hardware virtualisation, will be dual core and support SMT. Interesting, apparently virtualisation is not suited for multithreading.

To quote from the article:

Unfortunately, the process of binary translation usually reduces the amount of parallelism in the instruction stream because the translator only looks at a small snippet of code at a time, whereas a compiler can examine the entire application. Consequently, a very wide issue CPU like the POWER4/5 will have little parallelism to work with and relatively low performance. Narrower, faster CPUs are a much better fit with a workload that involves binary translation; both out of order execution and simultaneous multithreading will help as well.
 
Again, there are now non-binary translation virtualization techniques, which do not have that problem (though they still do not have much multithreading SMP support anyway). But SMP support has started coming in on both sides.
 
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