The Xbox 360 CPU architecture
The Xbox 360 system has a single chip (with 165 million transistors) for its CPU. This chip is in fact a three-way symmetric multiprocessor design. The three PowerPC cores are identical, except that they are physically reflected through the X and Y axis. Each of the CPU cores is a specialized PowerPC chip with a VMX128 extension related to (and partially compatible with) the VMX instructions in the G4 and G5 CPUs. The three CPU cores share a 1MB Level2 cache. Each processor has 32KB each of data and instruction Level1 cache. The chip's front-side bus/physical interface has a 21.6GB/second bandwidth, and runs at 5.4GHz. The high frequency clocks are generated on-chip by four phase-locked loops: two for the core clocks, two for the PHY clock.
The Xbox 360 CPU chip has testing and debug functions, including tracing, configuration control, and performance monitoring features. Access to these functions is through the block in Figure 1 labeled test/debug. The block labeled Miscellaneous IO provides a JTAG port, a POST monitor, and an interface for a serial EEPROM in case patch logic configuration was needed during bring-up.
To improve manufacturing yield, the SRAM Arrays used in the L1 and L2 caches support both row and column redundancy. This redundancy is enabled at chip test by burning electronic fuses. The eFuses are one of the unique capabilities of the IBM 90nm CMOS SOI technology the chip is fabricated in. Efuses were also used to record a unique supply voltage to be used for each chip. Finally, to help reduce the potential impact of process variations on the operation of the PHY analog circuits, eFuses were used for parametric adjustment in the analog units.
The physical package of the chip matters, too. A crucial design goal in the CPU of a consumer electronics device is high volume with good yield and comparatively low cost. The package is a 2-2-2 FC-PBGA, measuring 31mm by 31mm.
